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1 ? fn2856.4 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved all other trademarks mentioned are the property of their respective owners. ha-2420, HA-2425 3.2 s sample and hold amplifiers the ha-2420 and HA-2425 is a monolithic circuit consisting of a high performance operational amplifier with its output in series with an ultra-low leakage analog switch and jfet input unity gain amplifier. with an external hold capacit or connected to the switch output, a versatile, high performance sample-and-hold or track-and-hold circuit is formed. when the switch is closed, the device behaves as an operat ional amplifier, and any of the standard op amp feedback networks may be connected around the device to control gai n, frequency response, etc. when the switch is opened the ou tput will remain at its last level. performance as a sample-and-hold compares very favorably with other monolithic, hybrid, modular, and discrete circuits. accuracy to better than 0.01% is achievable over the temperature range. fast acquisi tion is coupled with superior droop characteristics, even at high temperatures. high slew rate, wide bandwidth, and low acquisition time produce excellent dynamic characteristi cs. the ability to operate at gains greater than 1 frequentl y eliminates the need for external scaling amplifiers. the device may also be used as a versatile operational amplifier with a gated output fo r applications such as analog switches, peak holding circuits, etc. for more information, please see application note an517. the mil-std-883 data sheet for this device is available on request. features ? maximum acquisition time - 10v step to 0.1% . . . . . . . . . . . . . . . . . . . . . 4 s (max) - 10v step to 0.01% . . . . . . . . . . . . . . . . . . . . 6 s (max) ? low droop rate (c h = 1000pf). . . . . . . . . . 5 v/ms (typ) ? gain bandwidth product . . . . . . . . . . . . . . . 2.5mhz (typ) ? low effective aperture delay ti me . . . . . . . . . 30ns (typ) ? ttl compatible control input ? 12v to 15v operation applications ? 12-bit data acquisition ? digital to analog deglitcher ? auto zero systems ? peak detector ? gated operational amplifier pinout ordering information part number temp. range ( o c) package pkg. dwg. # ha1-2420-2 -55 to 125 14 ld cerdip f14.3 ha1-2425-5 0 to 75 14 ld cerdip f14.3 ha3-2425-5 0 to 75 14 ld pdip e14.3 ha-2420 (cerdip) HA-2425 (cerdip, pdip) top view -in +in offset adj. offset adj. v- nc output s /h control gnd nc hold cap. nc v+ nc 1 2 3 4 5 6 7 14 13 12 11 10 9 8 data sheet july 2003
2 absolute maximum rati ngs thermal information voltage between v+ and v- terminals . . . . . . . . . . . . . . . . . . . .40v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24v digital input voltage (sample and hold pin) . . . . . . . . . . +8v, -15v output current . . . . . . . . . . . . . . . . . . . . . . . . short circuit protected operating conditions temperature range ha-2420-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c HA-2425-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 75 o c supply voltage range (typical) . . . . . . . . . . . . . . . . 12v to 15v thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) cerdip package. . . . . . . . . . . . . . . . . 75 20 pdip package . . . . . . . . . . . . . . . . . . . 95 n/a maximum junction temperature (ceramic packages) . . . . . . .175 o c maximum junction temperature (plastic package) . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mounted on a low effective ther mal conductivity test board in free air. see tech brief tb379 fo r details. electrical specifications test conditions (unless otherwise specified) v supply = 15.0v; c h = 1000pf; digital input: v il = +0.8v (sample), v ih = +2.0v (hold), unity gain configuration (output tied to negative input) parameter test conditions temp. ( o c) ha-2420-2 HA-2425-5 units min typ max min typ max input characteristics input voltage range full 10 - - 10 - - v offset voltage 25 - 2 4 - 3 6 mv full - 3 6 - 4 8 mv bias current 25 - 40 200 - 40 200 na full - - 400 - - 400 na offset current 25 - 10 50 - 10 50 na full - - 100 - - 100 na input resistance 25 5 10 - 5 10 - m ? common mode range full 10 - - 10 - - v transfer characteristics large signal voltage gain r l = 2k ? , v o = 20v p-p full 25 50 - 25 50 - kv/v common mode rejection v cm = 10v full 80 90 - 74 90 - db hold mode feedthrough attenuation (note 2) f in 100khz full - -76 - - -76 - db gain bandwidth product (note 2) 25 - 2.5 - - 2.5 - mhz output characteristics output voltage swing r l = 2k ? full 10 - - 10 - - v output current 25 15 - - 15 - - ma full power bandwidth (note 2) v o = 20v p-p 25 - 100 - - 100 - khz output resistance dc 25 - 0.15 - - 0.15 - ? transient response rise time (note 2) v o = 200mv p-p 25 - 75 100 - 75 100 ns overshoot (note 2) v o = 200mv p-p 25 - 25 40 - 25 40 % slew rate (note 2) v o = 10v p-p 25 3.5 5 - 3.5 5 - v/ s ha-2420, HA-2425
3 digital input characteristics digital input current v in = 0v full - - -0.8 - - -0.8 ma v in = 5v full - - 20 - - 20 a digital input voltage low full - - 0.8 - - 0.8 v high full 2.0 - - 2.0 - - v sample and hold characteristics acquisition time (note 2) to 0.1% 10v step 25 - 2.3 4 - 2.3 4 s acquisition time (note 2) to 0.01% 10v step 25 - 3.2 6 - 3.2 6 s hold step error v in = 0v 25 - 10 20 - 10 20 mv hold mode settling time to 1mv 25 - 860 - - 860 - ns aperture time (note 3) 25 - 30 - - 30 - ns effective aperture delay time 25 - 30 - - 30 - ns aperture uncertainty 25 - 5 - - 5 - ns drift current (note 2) v in = 0v 25 - 5 - - 5 - pa ha1-2420 full - 1.8 10 - - - na ha1-2425 full - - - - 0.1 1.0 na ha3-2425, ha4p2425, ha9p2425 full - - - - 7.5 10.0 na power supply characteristics supply current (+) 25 - 3.5 5.5 - 3.5 5.5 ma supply current (-) 25 - 2.5 3.5 - 2.5 3.5 ma power supply rejection full 80 90 - 74 90 - db notes: 2. a v = 1, r l = 2k ? , c l = 50pf. 3. derived from computer simulation only; not tested. functional diagram electrical specifications test conditions (unless otherwise specified) v supply = 15.0v; c h = 1000pf; digital input: v il = +0.8v (sample), v ih = +2.0v (hold), unity gain configuration (output tied to negative input) (continued) parameter test conditions temp. ( o c) ha-2420-2 HA-2425-5 units min typ max min typ max 4 3 offset adjust v+ 9 13 5 14 2 1 control s /h +input -input gnd v- ha-2420/2425 7 out 11 hold capacitor + - + - ha-2420, HA-2425
4 test circuits and waveforms figure 1. hold step error and drift current figure 2. hold step error test figure 3. drift current test figure 4. hold mode feedthrough attenuation -in +in s /h control output input s /h control input hold cap gnd c h s /h output control v step hold sample note: set rise/fall times of s /h control to approximately 20ns. output s /h control hold sample ? v ? t note: measure the slope of the output during hold, ? v/ ? t, and compute drift current from: i d = c h ? v/ ? t. in2 in1 in3 in4 in5 in6 in7 in8 a2 a1 a0 en out hi-508a mux +5v sine wave input s /h control input -in +in out v o s /h control hold cap gnd c h v inp-p ha-2420/2425 note: compute hold mode feedthrough attenuation from the formula: where v out hold = peak-to-peak value of output sinewave during the hold mode. feedthrough attenuation 20 v out hold v in hold ---------------------------------- log = ha-2420, HA-2425
5 schematic diagram s /h control gnd r p d 1 q 3 q 8 q 7 r 11 q 12 q 14 q 10 q 13 q 103 q 16 q 105 q 9 q 11 q 82 q 106 q 5 q 17 q 18 q q 15 q 2 q 4 q 6 q 21 q 20 q 22 q 23 q 26 q 25 q 24 q 27 r 1 q 29 r 2 q 30 q 31 q 35 q 38 r 13 q 33 q 34 q 32 q 39 q 40 q 41 q 44 q 43 q 42 offset adj. q 56 q 100 q 101 q 55 q 83 q 50 q 48 q 45 q 46 q 51 q 59 q 58 r 7 q 54 q 53 q 52 c 4 j 60 q 64 q 65 q 66 v+ c h q 72 q 73 q 74 out r 9 r 8 q 75 c 3 15pf q 77 q 76 q 68 q 78 q 67 q 69 r 10 q 70 q 79 q 102 v- -in r 14 q 80 q 81 q 71 q 62 19 q 83 q 91 q 90 q 89 q 87 +in q 47 q 49 j 61 j 63 j 57 gnd r 121 j 86 ha-2420, HA-2425
6 application information offset adjustment the offset voltage of the ha-2420 and HA-2425 may be adjusted using a 100k ? trim pot, as shown in figure 8. the recommended adjustment procedure is: apply 0v to the sample-and-hold input, and a square wave to the s /h control. adjust the trim pot for 0v output in the hold mode. gain adjustment the linear variation in pedestal voltage with sample-and- hold input voltage causes a -0.06% gain error (c h = 1000pf). in some applications (d/a deglitcher, a/d converter) the gain error can be adjusted elsewhere in the system, while in other applications it must be adjusted at the sample-and-hold. the two circuits shown below demonstrate how to adjust gain error at the sample-and-hold. the recommended procedure for adjusting gain error is: 1. perform offset adjustment. 2. apply the nominal input voltage that should produce a +10v output. 3. adjust the trim pot for +10v output in the hold mode. 4. apply the nominal input voltage that should produce a -10v output. 5. measure the output hold voltage (v -10nominal ). adjust the trim pot for an output hold voltage of figure 8 shows a typical unity gain circuit, with offset zeroing. all of the other normal op amp feedback configurations may be used with the ha-2420, HA-2425. the input amplifier may be used as a gated amplifier by utilizing pin 11 as the output. this amplifier has excellent drive capabilities along with exceptionally low switch leakage. the method used to reduce leakage paths on the pc board and the device package is shown in figure 9. this guard ring is recommended to minimize the drift during hold mode. the hold capacitor should have extremely high insulation resistance and low dielectric absorption. polystyrene (below 85 o c), teflon, or parlene types are recommended. for more applications, consult intersil application note an517, or the factory applications group. 0 +10 5 -5 -10 -15 -20 -25 -30 -35 -10 -5 +5 +10 dc input voltage (v) hold step voltage (mv) c h = 100pf c h = 1000pf c h = 10,000pf c h = 0.1 f figure 5. hold step vs input voltage v 10 ? nominal () -10v () + 2 ----------------------------------------------------------------- -in +in out s /h control output r i r f 0.002r f input s /h control input note: gain r f ? r i ---------- - figure 6. inverting configuration +in -in out s /h control output input s /h control input note: gain ~ 1 r f r i ------- - + r f r i 0.002r i figure 7. non-inverting configuration in v- 100k ? offset trim ( 25mv range) out v+ control c h - + - + figure 8. basic sample-and-hold (top view) ha-2420, HA-2425
7 glossary of terms acquisition time the time required following a ?sam ple? command, for the output to reach its final value within 0.1% or 0.01%. this is the minimum sample time required to obtain a given accuracy, and includes switch delay time, slewing time and settling time. aperture time the time required for the sample-and-hold switch to open, independent of delays through the switch driver and input amplifier circuitry. the switch opening time is that interval between the conditions of 10% open and 90% open. effective aperture delay time (eadt) the difference between the digital delay time from the hold command to the opening of the s/h switch, and the propagation time from the analog input to the switch. eadt may be positive, negative or zero. if zero, the s/h amplifier will output a voltage equal to v in at the instant the hold command was received. for negative eadt, the output in hold (exclusive of pedestal and droop errors) will correspond to a value of v in that occurred before the hold command. aperture uncertainty the range of variation in ef fective aperture delay time. aperture uncertainty (also called aperture delay uncertainty, aperture time jitter, etc.) sets a limit on the accuracy with which a waveform can be reconstructed from sample data. drift current the net leakage current from the hold capacitor during the hold mode. drift current can be calculated from the droop rate using the formula: -in +in v- v+ gnd control out hold capacitor figure 9. guard ring layout (bottom view) i d (pa) c h (pf) ? v ? t ------- - (v s ) ? = ha-2420, HA-2425
8 typical performance curves figure 10. typical sample and hold performance as a function of holding capacitor figure 11. broadband noise characteristics figure 12. drift current vs temperature figure 13. open loop frequency response figure 14. hold mode feed through attenuat ion figure 15. open loop phase response c h value 10pf 100pf 1000pf 0.01 f0.1 f1.0 f 1000 100 10 1.0 0.1 0.01 drift during hold at 25 o c (mv/s) slew rate (v/ s) hold step offset error (mv) unity gain bandwidth (mhz) unity gain phase margin (degrees) min. sample time for 0.1% accuracy 10v swings ( s) 1000 100 10 1 noise ( v rms ) 10 100 1k 10k 100k 1m bandwidth (lower 3db frequency = 10hz) output noise ?hold? mode equiv. input noise ?sample? mode - 0 ? source resistance equiv. input noise ?sample? mode - 100k ? source resistance 1000 100 10 1 i d (pa) -50 -25 0 25 50 75 100 125 temperature ( o c) 100 90 80 70 60 50 40 30 20 10 0 -10 -20 -30 10 100 1k 10k 100k 1m 10m 100m frequency (hz) open loop voltage gain (db) c h = 100pf c h = 1000pf c h = 0.01 f c h = 1.0 f c h = 0.1 f -30 -40 -50 -60 -70 -80 -90 100 1k 10k 100k 1m 10m 10v sinusoidal input frequency (hz) attenuation (db) c h = 1000pf 0 20 40 60 80 100 120 140 160 180 200 220 240 open loop phase angle (degrees) 10 100 1k 10k 100k 1m 10m 100m frequency (hz) c h = 0.01 f c h = 1000pf c h 100pf c h = 0.1 f c h = 1.0 f s /h control sample hold 4v 0v ha-2420, HA-2425
9 figure 16. acquisition time (c h = 1000pf) figure 17. acquisition time (c h = 1000pf) figure 18. acquisition time (c h = 1000pf) figure 19. acquisition time (c h = 1000pf) figure 20. acquisition time (c h = 1000pf) figure 21. acquisition time (c h = 1000pf) typical performance curves (continued) s /h 0v -10v (2v/div.) v out (5v/div.) time (1 s/div) 0v s /h +10v (2v/div.) v out (5v/div.) time (1 s/div) 0v time (1 s/div) s /h -1v (0.5v/div.) v out (5v/div.) 0v +1v time (1 s/div) s /h (0.5v/div.) v out (5v/div.) 0v time (500ns/div) s /h -0.1v (50mv/div.) v out (5v/div.) 0v time (500ns/div) s /h 0.1v (50mv/div.) v out (5v/div.) ha-2420, HA-2425
10 die characteristics die dimensions: 102 mils x 61 mils x 19 mils 2590 m x 1550 m x 483 m metallization: type: al, 1% cu thickness: 16k ? 2k ? substrate potential: v- backside finish: gold, nickel, silicon, etc. passivation: type: nitride (si 3 n 4 ) over silox (sio 2 , 5% phos.) silox thickness: 12k ? 2k ? nitride thickness: 3.5k ? 1.5k ? transistor count: 78 process: bipolar dielectric isolation metallization mask layout ha-2420, HA-2425 +in in gnd hold cap v+ v- vos adj vos adj output ha-2420, HA-2425
11 ha-2420, HA-2425 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpen- dicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not incl ude dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e14.3 (jedec ms-001-aa issue d) 14 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8 c 0.008 0.014 0.204 0.355 - d 0.735 0.775 18.66 19.68 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n14 149 rev. 0 12/93
12 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com ha-2420, HA-2425 ceramic dual-in-line fr it seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead di mensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this co nfiguration dimension b3 replaces dimension b2. 5. this dimension allows for off- center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa ca - b m d s s e a f14.3 mil-std-1835 gdip1-t14 (d-1, configuration a) 14 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.785 - 19.94 5 e 0.220 0.310 5.59 7.87 5 e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 6 s1 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2, 3 n14 148 rev. 0 4/94

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